1. Technical Field
The present invention relates to a static electricity protection circuit that protects an internal circuit of a semiconductor integrated circuit device from ESD (Electro-Static Discharge). The invention furthermore relates to a semiconductor integrated circuit device in which such a static electricity protection circuit is installed, and an electronic apparatus using such a semiconductor integrated circuit device.
2. Related Art
In a semiconductor integrated circuit device, a static electricity protection circuit is provided in order to prevent breakdown of the internal circuit caused by static electricity charged in a human body, a conveying apparatus, or the like being applied to the internal circuit. For example, the static electricity protection circuit is connected between a first terminal to which a high-potential-side power source potential is supplied and a second terminal to which a low-potential-side power source potential is supplied. When a positive charge is applied to the first terminal by electrostatic discharge or the like, the positive charge is discharged to the second terminal via the static electricity protection circuit, and therefore breakdown of the internal circuit can be prevented without an excessively large voltage being applied to the internal circuit.
As a related technique, FIG. 9 of JP-A-2009-182119 shows a known electrostatic discharge protection circuit that is connected between a high-potential-side first power source line and a low-potential-side second power source line. This electrostatic discharge protection circuit includes a time constant circuit 101 composed of a resistor and a capacitor connected in series between the first power source line and the second power source line, a discharge circuit composed of an N-channel transistor 102 connected between the first power source line and the second power source line, and three-stage inverters 103 to 105, whose input side is connected to the connection node of the resistor and the capacitor, and whose output side is connected to the gate of the transistor 102.
In the electrostatic discharge protection circuit, when a positive charge is applied to the first power source line, if the rising time of the potential of the first power source line is shorter than the time corresponding to the time constant of the time constant circuit 101, the potential at the connection node of the resistor and the capacitor is maintained at a low level. In this period, the gate of the transistor 102 reaches a high level, and the transistor 102 enters the on state. Accordingly, the positive charge applied to the first power source line is discharged to the second power source line, and the internal circuit is protected.
JP-A-2009-182119 is an example of related art (see paragraphs 0003 to 0010, FIG. 9).
However, with the electrostatic discharge protection circuit shown in FIG. 9 of JP-A-2009-182119, current starts to flow to the transistor 102 starting from an operation region in which the voltage between the first power source line and the second power source line is lower than a minimum operation voltage of the internal circuit. Accordingly, if the power source voltage rises sharply when the power source is turned on, there is a risk that the electrostatic discharge protection circuit will start the discharge operation and the internal circuit will malfunction. This kind of electrostatic discharge protection circuit needs to be used with a limit provided on the rising time of the power source voltage at the time of turning on the power source.
Also, during a normal operation in which the power source voltage is supplied between the first power source line and the second power source line, the capacitor is charged via the resistor of the time constant circuit 101, and therefore the input terminal of the inverter 103 is pulled up. Accordingly, there is a risk that even if noise, a discharged charge, or the like is applied from the exterior, the inverter 103 will not operate, the gate of the N-channel transistor 102 will remain at the low level, and therefore the discharge operation will not be performed. As a result, there is a problem in that the N-channel transistor 102 or the internal circuit breaks down.